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1 ? fn8148.0 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005. all rights reserved all other trademarks mentioned are the property of their respective owners. x80000, X80001 smart power plug? penta-power sequence controller with hot swap the x80000 contains three major functions: a power communications controller, a power sequencing controller, and a hotswap controller. the power communications controller allows smart power supply control via the backplane using the smbus protocol. the system can check for voltage, current, and manufacturing id compliance before board insertion. the power distribution network can monitor the status of the negative voltage supply, dc voltage supplies, and hardshort events by accessing the fault detection register and general purpose eeprom of the device. each device has a unique slave address for identification. the power sequencer controller time sequences up to five dc-dc modules. the x80000 allows for various hardwired configurations, either parallel or relay sequencing modes. the power good, enable and voltage good signals provide for flexible dc-dc timing configurations. each voltage enable signal has a programmable delay. in addition, the voltage good signals can be monitored remotely via the fault detection register (thru the smbus). the hot swap controller allows a board to be safely inserted and removed from a live backplane without turning off the main power supply. the x80000 family of devices offers a modular, power distribution approa ch by providing flexibility to solve the hotswap and power sequencing issues for insertion, operations, and ex traction. hardshort detection and retry with delay, noise filtering, insertion overcurrent bypass, and gate current selection are some of the programmable features of the device. during insertion, the gate of an external power mosfet is clamped low to suppress contact bounce. the undervoltage/overvoltage circuits and the power on reset circuitry suppress the gate turn on until the mechanical bounce has ended. the x80000 turns on the gate with a user set slew rate to limit the inrush current a nd incorporates an electronic circuit breaker set by a sense resistor. after the load is successfully charged, the pwrgd signal is asserted; indicating that the device is ready to power sequence the dc-dc power bricks. features ? integrates three major functions - smart power plug communications - programmable power sequencing - programmable hot swap controller ? smart power plug? - intelligent board insertion allows verification of board and power supply resources prior to system insertion. - fault detection register records the cause of the faults - soft extraction - soft re-insertion - remote gate shutdown/turn on - power id/manufacturing id memory (2kb of eeprom) ? programmable power sequencing - sequence up to 5 dc/dc converters. - four independent voltage enable pins - four programmable time delay circuits - soft power sequencing - restart sequence without power cycling. ? hot swap controller - programmable overvoltage and undervoltage protection - undervoltage lockout for battery/redundant supplies - programmable slew rate for external fet gate control - electronic circuit breaker - overcurrent detection and gate shut-off - programmable overcurrent limit during insertion - programmable hardshort retry with retry failure flag - typically operates from -30v to -80v. tolerates transients to -200v (limited by external components) ? available packages - 32-lead quad no-lead frame (qfn) applications ? -48v hot swap power backplane/distribution central office, ethernet for voip ? card insertion detection ? power sequencing dc-dc/power bricks ? ip phone applications ? databus power interfacing ? custom industrial power backplanes ? distributed power systems data sheet march 18, 2005
2 fn8148.0 march 18, 2005 pinout x80000, X80001 (7x7 qfn) top view typical application v1good mrc a0 v3good v2good en4 en3 en1 reset wp v4good drain pwrgd sense v uv/ov i gq0 v ee gate v dd far batt-on mrh i gq1 scl 1 2 3 4 5 6 7 91011 12 13 14 18 19 20 21 22 23 24 26 27 28 29 30 31 32 sda en2 817 nc v ee 15 25 v rgo 16 a1 nc nc (7mm x 7mm) ordering information part number ov uv1 uv2 temp range pkg part mark x80000q32i 74.9 42.4 33.2 i 32 ld qfn 80000i X80001q32i 68.0 42.4 33.2 i 32 ld qfn 80001i v dd x80000 v uv/ov v ee sense drain -48v uv=37v ov=71v -48v gate rs 0.02 ? 5% r4 182k 1% r5 30k 1% r6 10k 1% q1 irfr120 rtn 100k v1good v2good v3good dc-dc module 1 on /off dc-dc module 2 on /off dc-dc module 3 on /off dc-dc module 4 on /off pwrgd en1 en2 en3 scl scl 4.7v 12v X80001 v1 v2 v3 v4 100 0.1f sda back- plane sda mrh opto- isolation insert control 4.7k 3.3n x80000, X80001
3 fn8148.0 march 18, 2005 absolute maximum ratings recommended operating conditions temperature under bias . . . . . . . . . . . . . . . . . . . . . ?65c to +135c storage temperature . . . . . . . . . . . . . . . . . . . . . . . ?65c to +150c voltage on given pin (hot side functions): v ov/uv pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5v + v ee sense pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400mv + v ee v ee pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -80v drain pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48v + v ee pwrgd pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7v + v ee gate pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dd + v ee far pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7v + v ee mrh pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5v + v ee batt_on pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5v + v ee voltage on given pin (cold side functions): eni pins (i = 1 to 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5v vigood pins (i = 1 to 4) . . . . . . . . . . . . . . . . . . . . . . .5.5v + v ee reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5v + v ee sda, scl, wp, a0, a1 pins . . . . . . . . . . . . . . . . . . . . .5.5v + v ee mrc pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5v + v ee igq1 and igq0 pins . . . . . . . . . . . . . . . . . . . . . . . . . .5.5v + v ee v dd pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14v + v ee d.c. output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ma lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . . 300c temperature range (industrial) . . . . . . . . . . . . . . . . . . -40c to 85c supply voltage (v dd ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12v caution: stresses above those listed under ?absolute maximum rati ngs? may cause permanent damage to the device. this is a stres s rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. electrical specifications standard settings over the recommended operating conditi ons unless otherwise specified. symbol parameter test conditions min typ max unit dc characteristics v dd supply operating range 10 12 14 v i dd supply current 2.5 5 ma v rgo regulated 5v output i rgo = 10a 4.5 5.5 i rgo v rgo current output 50 a i gate gate pin current gate drive on, v gate = v ee , v sense = v ee (sourcing) 46.2 52.5 58.8 a v gate - v ee = 3v v sense -v ee = 0.1v (sinking) 9ma v gate external gate drive (slew rate control) i gate = 50a v dd -0.01 v dd v v pga power good threshold (pwrgd high to low) referenced to v ee v uv1 < v uv/ov < v ov 0.9 1 1.1 v v ihb voltage input high (batt_on) v ee + 4 v ee + 5 v v ilb voltage input low (batt_on) v ee + 2 v i li input leakage current (mrh , mrc) v il = gnd to v cc 10 a i lo output leakage current (v1good , v2good , v3good , v4good , reset ) all eni = v rgo for i = 1 to 4 10 a v il input low voltage (mrh , mrc, igq0, igq1) -0.5 + v ee (v ee + 5) x 0.3 v v ih input high voltage (mrh , mrc, igq0, igq1) (v ee + 5) x 0.7 (v ee + 5) + 0.5 v x80000, X80001
4 fn8148.0 march 18, 2005 v ol output low voltage (reset , v1good , v2good , v3good , v4good, far , pwrgd ) i ol = 4.0ma v ee + 0.4 v c out (note 1) output capacitance (reset , v1good , v2good , v3good , v4good , far ) v out = 0v 8 pf c in (note 1) input capacitance (mrh , mrc) v in = 0v 6 pf v oc overcurrent threshold v oc = v sense - v ee 45 50 55 mv v oci overcurrent threshold (insertion) v oc = v sense - v ee pwrgd = high initial power up condition 135 150 165 mv v ovr overvoltage threshold (rising) x80000 referenced to v ee 3.85 3.90 3.95 v X80001 3.49 3.54 3.59 v v ovf overvoltage threshold (falling) x80000 referenced to v ee 3.82 3.87 3.92 v X80001 3.46 3.51 3.56 v v uv1r undervoltage 1 threshold (rising) referenced to v ee batt-on = v ee 2.19 2.24 2.29 v v uv1f undervoltage 1 threshold (falling) 2.16 2.21 2.26 v v uv2r undervoltage 2 threshold (rising) referenced to v ee batt-on = v rgo 1.71 1.76 1.81 v v uv2f undervoltage 2 threshold (falling) 1.68 1.73 1.78 v v drainf drain sense voltage threshol d (falling) referenced to v ee 0.9 1 1.1 v v drainr drain sense voltage thres hold (rising) referenced to v ee 1.2 1.3 1.4 v v trip1 (note 1) en1 trip point voltage referenced to v ee v rgo 2 v v trip2 (note 1) en2 trip point voltage referenced to v ee v v trip3 (note 1) en3 trip point voltage referenced to v ee v v trip4 (note 1) en4 trip point voltage referenced to v ee v ac characteristics t foc sense high to gate low 1.5 2.5 3.5 s t fuv under voltage conditions to gate low 0.5 1 1.5 s t fov overvoltage conditions to gate low 1.0 1.5 2 s t vfr overvoltage/undervoltage failure recovery time to gate =1v. v dd does not drop below 3v, no other failure conditions. 1.2 1.6 2 s t batt_on delay batt_on valid 100 ns t mrc minimum time high for reset valid on the mrc pin 5 s t mrh minimum time high for reset valid on the mrh pin 5 s t mrce delay from mrc enable to pwrgd high no load 1.0 1.6 s t mrcd delay from mrc disable to pwrgd low gate is on, no load 200 400 ns t mrhe delay from mrh enable to gate pin low i gate = 60a, no load 1.0 1.6 2.4 s electrical specifications standard settings over the recommended operating conditi ons unless otherwise specified. (continued) symbol parameter test conditions min typ max unit x80000, X80001
5 fn8148.0 march 18, 2005 equivalent a.c. out put load circuit t mrhd delay from mrh disable to gate reaching 1v i gate = 60a, no load 1.8 2.6 s t reset _e delay from pwrgd or vigood to reset valid low 1 s t qc delay from igq1 and igq0 to valid gate pin current 1 s t sc_retry delay between retries tsc1 = 0; tsc0 = 0 90 100 110 ms t nf noise filter for overcurrent tf1 = 0; tf0 = 1 4.5 5 5.5 s t dpor device delay before gate assertion 45 50 55 ms t spor delay after pwrgd and all vigood signals are active before reset assertion tpor1 = 0; tpor0 = 0 90 100 110 ms t to vigood turn off time 50 ns t pdhlpg (note 1) delay from drain good to pwrgd low gate = v dd 1 s t pdlhpg (note 1) delay from drain fail to pwrgd high gate = v dd 1 s t pghlpg (note 1) delay from gate good to pwrgd low drain = v ee 1 s t pglhpg (note 1) delay from gate fail to pwrgd high drain = v ee 1 s note: 1. this parameter is based on characterization data. electrical specifications standard settings over the recommended operating conditi ons unless otherwise specified. (continued) symbol parameter test conditions min typ max unit a.c. test conditions input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing levels v cc x 0.5 output load standard output load 5v sda 30pf 4.6k ? reset 30pf v1good , 5v 4.6k ? 30pf v2good , v3good , v4good , far 5v 4.6k ? pwrgd x80000, X80001
6 fn8148.0 march 18, 2005 sense v uv/ov v ov v uv v dd v th mrh gate v oc v oci t vfr t fov t fuv t dpor t vfr 1v 1v figure 1. overvoltage/undervoltage gate timing sense v dd v th gate v oc v oci t dpor t sc_retry t foc t foc always retry v uv < v uv/ov < v ov t sc_retry mrh = high figure 2. overcurrent gate timing eni t to vigood v tripi t delayi i = 1, 2, 3, 4 initial power-up t to v dd enable dc/dc supply figure 3. vigood timings x80000, X80001
7 fn8148.0 march 18, 2005 t mrhd gate t mrhe mrh t mrh 1v figure 4. manual reset (hot side) mrh t mrcd pwrgd mrc t mrce t mrc figure 5. manual reset (cold side) mrc pwrgd t delay1 v1good t delay2 v2good t delay3 v3good t delay4 v4good t spor reset t reset _e pwrgd or any eni low to high v drain t glhpg t ghlpg (1st occurance) v gate t dlhpg t dhlpg eni figure 6. pwrgd and reset timings x80000, X80001
8 fn8148.0 march 18, 2005 electrical specifications programmable parameters over the recommended operating conditi ons unless otherwise specified. symbol parameter test conditions min. typ. max. unit dc characteristics vcb over current trip voltage range factory setting is 50mv (see voci). 30 100 mv i gate (v cb = v sense - v ee ) for other options, contact intersil. -12 12 % gate pin pull-up current. (error) (current) gate drive on; v gate = v ee , igq1=0; igq0=0 ig3 = 0; ig2= 0; ig1 = 0; ig0 = 0 factory default 9.2 10.5 11.8 a ig3 = 0; ig2= 0; ig1 = 0; ig0 = 1 21.0 a ig3 = 0; ig2= 0; ig1 = 1; ig0 = 0 31.5 a ig3 = 0; ig2= 0; ig1 = 1; ig0 = 1 42.0 a ig3 = 0; ig2= 1; ig1 = 0; ig0 = 0 46.2 52.5 58.5 a ig3 = 0; ig2= 1; ig1 = 0; ig0 = 1 63.0 a ig3 = 0; ig2= 1; ig1 = 1; ig0 = 0 64.7 73.5 82.3 a ig3 = 0; ig2= 1; ig1 = 1; ig0 = 1 84.0 a ig3 = 1; ig2= 0; ig1 = 0; ig0 = 0 94.5 a ig3 = 1; ig2= 0; ig1 = 0; ig0 = 1 105.0 a ig3 = 1; ig2= 0; ig1 = 1; ig0 = 0 115.5 a ig3 = 1; ig2= 0; ig1 = 1; ig0 = 1 126.0 a ig3 = 1; ig2= 1; ig1 = 0; ig0 = 0 136.5 a ig3 = 1; ig2= 1; ig1 = 0; ig0 = 1 147.0 a ig3 = 1; ig2= 1; ig1 = 1; ig0 = 0 138.6 157.5 176.4 a ig3 = 1; ig2= 1; ig1 = 1; ig0 = 1 168.0 a ig3-ig0 = don?t care igq1=0; igq0=1 9.2 10.57 11.8 a ig3-ig0 = don?t care igq1=1; igq0=0 64.7 73.5 82.3 a ig3-ig0 = don?t care igq1=1; igq0=1 138.6 157.5 176.4 a v pga power good threshold accuracy v drain - v ee , high to low transition. default factory setting is 47v. 400 mv v oci over current threshold (insertion) referenced to vee vs1 = 0 vs0 = 0 pwrgd = high 45 50 55 mv vs1 = 0 vs0 = 1 factory default 90 100 110 mv vs1 = 1 vs0 = 0 135 150 165 mv vs1 = 1 vs0 = 1 180 200 220 mv ac characteristics t sc_retry delay between retries factory default tsc1 = 0 tsc0 = 0 90 100 110 ms tsc1 = 0 tsc0 = 1 450 500 550 ms tsc1 = 1 tsc0 = 0 0.9 1 1.1 s tsc1 = 1 tsc0 = 1 4.5 5 5.5 s x80000, X80001
9 fn8148.0 march 18, 2005 t nf noise filter for overcurrents factory default f1 = 0 f0 = 0 0s f1 = 0 f0 = 1 4.5 5 5.5 s f1 = 1 f0 = 0 9 10 11 s f1 = 1 f0 = 1 18 20 22 s t spor delay before reset assertion factory default tpor1 = 0 tpor0 = 0 90 100 110 ms tpor1 = 0 tpor0 = 1 450 500 550 ms tpor1 = 1 tpor0 = 0 0.9 1 1.1 s tpor1 = 1 tpor0 = 1 4.5 5 5.5 s t delayi time delay used in power sequencing (i = 1 to 4) factory default tid1 = 0 tid0 = 0 90 100 110 ms tid1 = 0 tid0 = 1 450 500 550 ms tid1 = 1 tid0 = 0 0.9 1 1.1 s tid1 = 1 tid0 = 1 4.5 5 5.5 s serial interface over the recommended operating conditi ons unless otherwise specified. symbol parameter test conditions min typ max unit dc characteristics i cc1 (note 1) active supply current (v dd ) read to memory or crs v il = v cc x 0.1 v ih = v cc x 0.9, f scl = 400khz 2.5 ma i cc2 (note 1) active supply current (v dd ) write to memory or crs 3.0 ma i li input leakage current (scl, wp, a0, a1) v il = gnd to v cc 10 a i lo output leakage current (sda) v sda = gnd to v cc device is in standby (note 2) 10 a v il (note 3) input low voltage (sda, scl, wp, a0, a1) -0.5 + vee (v ee + 5) x 0.3 v v ih (note 3) input high voltage (sda, scl, wp, a0, a1) (v ee + 5) x 0.7 (v ee + 5) + 0.5 v v hys schmitt trigger input hysteresis fixed input level v ee + 0.2 v v cc related level .05 x (v ee + 5) v v ol output low voltage (sda) i ol = 4.0ma (2.7-5.5v) i ol = 2.0ma (2.4-3.6v) v ee + 0.4 v ac characteristics f scl scl clock frequency 400 khz t in pulse width suppression time at inputs 50 ns t aa scl low to sda data out valid 0.1 1.5 s electrical specifications programmable parameters over the recommended operating conditi ons unless otherwise specified. (continued) symbol parameter test conditions min. typ. max. unit x80000, X80001
10 fn8148.0 march 18, 2005 timing diagrams t buf time the bus is free before start of new transmission 1.3 s t low clock low time 1.3 s t high clock high time 0.6 s t su:sta start condition setup time 0.6 s t hd:sta start condition hold time 0.6 s t su:dat data in setup time 100 ns t hd:dat data in hold time 0 s t su:sto stop condition setup time 0.6 s t dh data output hold time 50 ns t r sda and scl rise time 20 +.1cb (note 1) 300 ns t f sda and scl fall time 20 +.1cb (note 1) 300 ns t su:wp wp setup time 0.6 s t hd:wp wp hold time 0 s cb capacitive load for each bus line 400 pf t wc (note 2) eeprom write cycle time 5 10 ms note: 2. t wc is the time from a valid stop condition at the end of a writ e sequence to the end of the self-timed internal nonvolatile write cycle. it is the minimum cycle time to be allowed for any nonvolatile write by the user, unless a cknowledge polling is used. serial interface (continued) over the recommended operating conditi ons unless otherwise specified. symbol parameter test conditions min typ max unit figure 7. bus timing t su:sto t high t su:sta t hd:sta t hd:dat t su:dat scl sda in sda out t f t low t hd:dat t r t dh t aa t buf t hd:sto t buf x80000, X80001
11 fn8148.0 march 18, 2005 symbol table t hd:wp scl sda in wp t su:wp clk 1 clk 9 slave address byte start figure 8. wp pin timing scl sda 8 th bit of last byte ack stop condition start condition figure 9. write cycle timing t wc must be steady will be steady may change from low will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known waveform inputs outputs to high x80000, X80001
12 fn8148.0 march 18, 2005 typical performance characteristics figure 10. overcurrent threshold vs temperature figure 11. undervoltage 1 threshold vs temperature figure 12. overvoltage threshold vs temperature figure 13. eni threshold vs temperature figure 14. undervoltage 1 threshold vs temperature figure 15. i gate (source) vs temperature 46.000 47.000 48.000 49.000 50.000 51.000 52.000 -55 -40 -25 -10 5 20 35 50 65 80 95 110 12 temperature inrush current limit (mv) 1.690 1.700 1.710 1.720 1.730 1.740 1.750 1.760 1.770 1.780 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature rising falling undervoltage 2 threshold (v) 3.85 3.86 3.87 3.88 3.89 3.90 3.91 3.92 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature rising falling ov threshold (v) 2.475 2.480 2.485 2.490 2.495 2.500 2.505 2.510 2.515 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature eni threshold (v) 2.190 2.200 2.210 2.220 2.230 2.240 2.250 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature rising falling undervoltage 1 threshold (v) 0 40 80 120 160 200 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature 150a 70a 50a 10a gate current (a) x80000, X80001
13 fn8148.0 march 18, 2005 figure 16. i gate (sink) vs temperature figure 17. t foc vs temperature figure 18. t fuv vs temperature figure 19. t delayi vs temperature figure 20. t fov vs temperature typical performance characteristics (continued) 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature gate current - sink (ma) 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature t oc (s) 0.500 0.550 0.600 0.650 0.700 0.750 0.800 -55-40-25-10 5 203550658095110125 temperature tuv1 tuv2 t uv (s) 0.90 0.92 0.94 0.96 0.98 1.00 1.02 -55 -35 -15 5 25 45 65 85 temperature t delay (normalized) 1.0 1.1 1.1 1.2 1.2 1.3 1.3 1.4 1.4 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature t ov (s) x80000, X80001
14 fn8148.0 march 18, 2005 sense v ee gate igq1 igq0 drain batt-on mrc mrh en1 en2 en3 en4 v4good v3good v2good v1good a1 a2 wp scl sda reset v dd far pwrgd power good logic slew rate selection eeprom 2kbits 5v v rgo bus interface v ee v ee v ee v ee v ee v ee v ov ref v uv1 ref v uv2 ref v uv/ov 2:1 mux v ee gate control v dd 1v ref v rgo programmable v oc ref 36r rrrr over current x1 x2 x3 x4 reset logic and delay v ee over current logic, hard short relay, retry logic status and delay por control and fault registers 10-160a divider 4 reset osc 0.1s 0.5s 1s 5s select 4 delay1 delay2 delay3 delay4 delay circuit repeated 4 times v rgo figure 21. block diagram x80000, X80001
15 fn8148.0 march 18, 2005 pin configuration v1good mrc a0 v3good v2good en4 en3 en1 reset wp v4good drain pwrgd sense v uv/ov i gq0 v ee gate v dd far batt-on mrh i gq1 scl 1 2 3 4 5 6 7 91011 12 13 14 18 19 20 21 22 23 24 26 27 28 29 30 31 32 x80000/X80001 32-lead qfn quad package sda en2 817 na v ee 15 25 v rgo 16 a1 nc nc (7mm x 7mm) pin descriptions pin name description 1v rgo regulated 5v output. used to pull-up user programmable inputs igq0, igq1, batt-on, a1, a0, and wp (if needed). 2a0 address select input. it has an internal pulldown resistor. (>10m ? typical) the a0 and a1 bits allow for up to 4 x80000 devices to be used on the same smbus serial interface. 3 v4good v4 voltage good output. this open drain output goes low when en4 is less than v trip4 and goes high when en4 is greater than v trip4 . there is a user selectable delay circuitry on this pin. 4en4 v4 voltage enable input. fourth voltage enable pin. if unused connect to v rgo . 5 v3good v3 voltage good output (active low). this open drain output goes low when en3 is less than v trip3 and goes high when en3 is greater than v trip3 . there is a user selectable delay circuitry on this pin. 6en3 v3 voltage enable input. third voltage enable pin. if unused connect to v rgo . 7 v2good v2 voltage good output (active low). this open drain output goes low when en2 is less than v trip2 and goes high when en2 is greater than v trip2 . there is a user selectable delay circuitry on this pin. 8en2 v2 voltage enable input. second voltage enable pin. if unused connect to v rgo . 9v dd positive supply voltage input. 10 v ee negative supply voltage input. 11 v uv/ov analog undervoltage and overvoltage input. turns off the external n-channel mosfet when there is an undervoltage or overvoltage condition. 12 sense circuit breaker sense input . this input pin detects the overcurrent condition. 13 gate gate drive output. gate drive output for the external n-channel mosfet. 14 drain drain . drain sense input of the external n-channel mosfet. 15 na not available. do not connect to this pin. 16 a1 address select input. it has an internal pulldown resistor. (>10m ? typical) the a0 and a1 bits allow for up to 4 x80000 devices to be used on the same smbus serial interface. 17 sda serial data. sda is a bidirectional pin used to transfer data into and out of the device. it has an open drain output and may be wire ored with other open drain or open collecto r outputs. this pin requires a pull up resistor and the input buffer is always active (not gated). 18 scl serial clock. the serial clock controls the serial bus timing for data input and output. 19 en1 v1 voltage enable input. first voltage enable pin. if unused connect to v rgo . x80000, X80001
16 fn8148.0 march 18, 2005 functional description hot circuit insertion when circuit boards are inserted into a live backplane, the bypass capacitors at the input of the board?s power module or dc/dc converter can draw huge transient currents as they charge up (see figure 22). this transient current can cause permanent damage to the board?s components and cause transients on the system power supply. the x80000 is designed to turn on a board?s supply voltage in a controlled manner (see figure 23), allowing the board to be safely inserted or removed from a live backplane. the device also provides undervoltage, overvoltage and overcurrent protection while keeping the power module (dc- dc converter) off until the backplane input voltage is stable and within tolerance. 20 v1good v1 voltage good output (active low). this open drain output goes low when en1 is less than v trip1 and goes high when en1 is greater than v trip1 . there is a user selectable delay circuitry on this pin. 21 reset reset output. this open drain pin is an active low out put. this pin will be active until pwrgd goes active and the power sequencing is complete. this pin will be released after a programmable delay. 22 wp write protect. input pin. wp high (in conjunction with wpen bi t=1) prevents writes to any memory location in the device. it has an internal pulldown resistor. (>10m ? typical) 23 mrc manual reset input cold-side. pulling the mrc pin high initiates a system side reset. the mrc signal must be held high for 5 secs. it has an internal pulldown resistor. (>10m ? typical) 24 nc no connect. no internal connections. 25 v ee negative supply voltage input. 26 nc no connect. no internal connections. 27 far failure after re-try (far ) output signal. failure after re-try (far ) is asserted after a number of retries. used for overcurrent and hardshort detection. 28 batt-on battery on input . this input signals that the battery backup (or secondary supply) is supplying power to the backplane. it has an internal pulldown resistor. (>10m ? typical) 29 pwrgd power good output. this output pin enables a power module. 30 igq1 gate current quick select bit 1 input. this pin is used to change the gate current drive and is intended to allow for current ramp rate control of the gate pin of an external fet. it has an internal pulldown resistor. (>10m ? typical) 31 igq0 gate current quick select bit 0 input. this pin is used to change the gate current drive and is intended to allow for current ramp rate control of the gate pin of an external fet. it has an internal pulldown resistor. (>10m ? typical) 32 mrh manual reset input hot-side. pulling the mrh pin low initiates a gate pin reset (gate pin pulled low). the mrh signal must be held low for 5 secs (minimum). pin descriptions (continued) pin name description v dd x80000 v uv/ov v ee sense drain -48v uv=37v ov=71v -48v gate rs 0.02 ? 5% r4 182k 1% r5 30k 1% r6 10k 1% q1 irfr120 return 100k -48v dc/dc converter dc/dc converter i inrush X80001 0.1f 100 4.7k 3.3n figure 22. typical -48v ho tswap application circuit v gate v fet_drain pwrgd i inrush figure 23. typical inrush with gate slew rate control x80000, X80001
17 fn8148.0 march 18, 2005 overvoltage and undervoltage shutdown the x80000 provides overvoltage and undervoltage protection circuits. when an overvoltage (v ov ) or undervoltage (v uv1 and v uv2 ) condition is detected, the gate pin will be immediately pulled low. the undervoltage threshold v uv1 applies to the normal operation with a main supply. the undervoltage threshold v uv2 assumes the system is powered by a battery. when using a battery backup, the batt-on pin is pulled to v rgo . the default thresholds have been set so the external resistance values determine the overvoltage threshold, a main undervoltage threshold and a battery undervoltage threshold. as shown in figure 26, this circuit block contains comparators and programmable voltage references to monitor the single overvoltage and dual undervoltage trip points. during manufacturing, intersil programmed the overvoltage and undervoltage trip points as shown in table 1 below. custom values are possible. a resistor divider connected between the plus and minus input voltages and the v uv/ov pin (see figure 24) determines the overvoltage and undervoltage shutdown voltages and the operating voltage range. using the thresholds in table 1 and the equations of figure 24 the desired operating voltage can be determined. figure 25 shows the resistance values for various operating voltages. battery back up operations an external signal, batt-on, is provided to switch the undervoltage trip point. the batt-on signal is a logic high if v ihb > v ee + 4v and is a logic low if v ilb < v ee + 2v. the time from a batt-on input change to a valid new undervoltage threshold is 100ns. see electrical specifications for more details. note: the v uv/ov pin must be limited to less than v ee + 5.5v in worst case conditions. values for r1 and r2 must be chosen such that this condition is met. intersil recommends r1 = 182k ? and r2 = 10k ? to conform to factory settings. overvoltage/undervoltage fault condition flags on any overvoltage or undervoltage violation, the x80000 cuts-off the gate. this condition also sets the fault- overvoltage (fov) or fault-undervoltage1/2 (fuv1/2) bits low. these bits are readable through the smbus. to clear the fault bits, the fault condition must first be rectified (by the table 1. overvoltage/undervoltage default thresholds threshold symbol description falling rising max/min voltage (note 1) lockout voltage (note 2) v ov overvoltage (x80000) 3.87v 3.9v 74.3 74.9 v ov overvoltage (X80001) 3.51v 3.54v 67.4 68 v uv1 undervoltage 1 2.21v 2.24v 43.0 42.4 v uv2 undervoltage 2 1.73v 1.76v 33.8 33.2 notes: 1. max/min voltage is the maximum and minimum operating voltage assuming the recommended v uv/ov resistor divider. 2. lockout voltage is the voltage where the x80000/1 turns off the fet. table 2. selecting between undervoltage trip points pin description trip point selection batt-on undervoltage trip point selection pin if batt-on = 0, v uv1 trip point is selected; if batt-on = 1, v uv2 trip point is selected. v uv1 and v uv2 are undervoltage thresholds. r1 r2 v p v uv/ov v n voltage divider: or: v uv ov ? v s r2 r1 r2 + ---------------------- ?? ?? = v s v uv ov ? r1 r2 + r2 ---------------------- ?? ?? = v s figure 24. overvoltage undervoltage divider batt-on = v ee v ov v uv1 v uv2 operating voltage batt-on = v rgo 100 90 80 70 60 50 40 30 20 10 0 150 158 166 175 182 190 198 206 214 222 operating voltage (v) r1 in k ? (for r2=10k) figure 25. operating voltage vs resistor ratio x80000, X80001
18 fn8148.0 march 18, 2005 system) then cleared by a write to fault detection register. please refer to fdr section. see table 2. overcurrent protection (circuit breaker function) the x80000 overcurrent circuit provides the following functions: ? overcurrent shut-down of the power fet and external power good indicators. ? noise filtering of the current monitor input. ? relaxed overcurrent limits for initial board insertion. ? overcurrent recovery retry operation. ? flag of overcurrent fault condition. ? flag of overcurrent retry failure. a sense resistor, placed in the supply path between v ee and sense (see figure 22) generates a voltage internal to the x80000. when this voltage exceeds 50mv, an over current condition exists and an internal ?circuit breaker? trips, turning off the gate drive to the external fet. the actual overcurrent level is dependent on the value of the current sense resistor. for example a 20m ? sense resistor sets the overcurrent level to 2.5a. intersil?s x80000 provides a safety mechanism during insertion of the board into the back plane. during insertion of the board into the backplane large currents may be induced. in order to prevent premature s hut down of the external fet, the x80000 allows for a choice of up to 4 times the overcurrent setting during insertion. after the pwrgd signal is asserted, the x80000 switches back to the normal overcurrent setting. the overcurrent threshold voltage during insertion can be changed from 50mv to 100mv, 150mv, or 200mv, by setting bits in control register cr4. after the power fet turns off due to an overcurrent condition, a retry circuit turns the fet back on after a delay of t sc_retry . if the overcurrent condition remains, the fet again turns off. this sequence repeats until the overcurrent condition is released. there ar e various other options that program the retry circuit to change the number of retries or to not retry. an optional output signal, far , indicates a failure after retry. overcurrent shut-down as shown in figure 27, this circuit block contains a resistor ladder, a comparator, a noise filter and a programmable voltage reference to monitor for overcurrent conditions. the overcurrent voltage threshold (v oc ) is 50mv. this can be factory set, by special or der, to any setting between 30mv and 100mv. v oc is the voltage between the sense and v ee pins and across the r sense resistor. if the selected sense resistor is 20m ? , then 50mv corresponds to an overcurrent of 2.5a. if an overcurrent condition is detected, the gate is turned off, all power good indicators go inactive and an overcurrent failure bit (foc) is set. overcurrent noise filter the x80000 has a noise (low pass) filter built into the overcurrent comparator. the comparator will thus ignore current spikes shorter than 5s . other filter options are provided by setting control bits in register cr4. the control bits set the comparator to ignore current spikes shorter that 5s, 10s or 20s and allow the filter to be turned off. table 3. overvoltage/undervoltage flag bits symbol violation (on) normal (off) fov fov = 0, when v uv/ov > v ov (overvoltage) fov = 1, when v uv/ov < v ov + 0.2v and reset by a write operation fuv1/2 fuv1/2 = 0, when v uv/ov < v uv1/2 (undervoltage) fuv1/2 = 1, when v uv/ov > v uv1/2 - 0.2v and reset by a write operation programmable vref control & status registers 2:1 mux -48v v uv/ov batt_on sda scl overvoltage flag uv flag_1 uv flag_2 uv flag r1=182k r2=10k v ov to gate to gate fault bits fov fuv1/2 + - - + - + programmable vref programmable vref v uv1 v uv2 smbus control control figure 26. programmable undervoltage and overvoltage for primary and battery backup table 4. noise filter for over currents f1 f0 t nf (maximum noise input pulse width) 00 0s 01 5s 10 10s 11 20s x80000, X80001
19 fn8148.0 march 18, 2005 overcurrent during insertion insertion is defined as the first plug-in of the board to the backplane. in this case, the x80000 is initially fully powered off prior to the hot plug connection to the mains supply. this condition is different from a situation where the mains supply has temporarily failed resultin g in a partial recycle of the power. this second condition will be referred to as a power cycle. during insertion, the board can experience high levels of current for short periods of time as power supply capacitors charge up on the power bus. to prevent the overcurrent sensor from turning off the fet inadvertently, the x80000 has the ability to allow more current to flow through the powerfet and the sense resistor for a short period of time until the fet turns on and the pwrgd signal goes active. in the standard setting, 200mv is allowed across sense resistor the during insertion (10a assuming a 20mw resistor). two bits in register cr4 select the insertion current limit of 1x, 2x, 3x or 4x the base setting of 50mv. this provides a mechanism to reduce insertion issues associated with huge current surges. hardshort protection - programmable retry in the event on an overcurrent or hard short condition, the x80000 includes a retry circuit. this circuit waits for 100ms, then attempts to again turn on the fet. if the fault condition still exists, the fet turns off and a retry counter (sc_counter) increments. after the selected number of failed trys, the x80000 sets a failed after retry status (far_stat) fault bit, sets the far pin low and goes into an idle state. in this state th e gate pin will not go active until the device is cleared. the retry circuit can be programmed to handle the retry operation in one of eight ways (see table 6). the options allow retries from zero to unlimited and specifies when to assert the far (failure after re-try) signal. in the ?always retry? case there is no idle state, so when the overcurrent condition clears, the gate go es active and the fet turns on. there are four optional retry delay periods. these are 100ms, 500ms, 1s, and 5s. these are programmed by bits located in the cr2 register. after far is asserted, there are two ways to clear the hardshort protection: 1. master reset hot side. the master reset pin, mrh , can be asserted by pulling it low. upon mrh assertion, all default values are restored and the retry is cleared. 2. power cycle the part, turning v dd off, then on. if an overcurrent condition does not occur on any retry, the gate pin will proceed to open at the user defined slew rate. overcurrent fault condition flags on any overcurrent violation, the x80000 will cut-off the gate, turning off the voltage to the load, and setting all power good pins to their disabled state. in this condition, the fault-overcurrent bit (foc) goes low. to clear foc, remove the over current conditi on, then write to the control register. refer to instructions on writing to the fdr (see table 8). table 5. insertion overcurrent threshold options vs1 vs0 v oci 0 0 50mv (1x) 0 1 100mv (2x) 1 0 150mv (3x) 1 1 200mv (4x) 2 bit noise filtering control registers sda scl overcurrent logic and gate control block short-circuit retry logic and system monitors far failure after re-try retry delay retry counter n retry fault bit far_stat programmable voltage reference 0s 5s 10s 20s 36r 4x 3x 2x 1x r r r r + ? -48v overcurrent event r sense smbus v ee figure 27. overcurrent detection/short circuit protection with programmble retry and flag monitors x80000, X80001
20 fn8148.0 march 18, 2005 when exceeding the overcurrent retry limit, the status bit ?far_stat? is set to ?1? and the far pin is asserted. to clear far_stat, write to the control register. refer to instructions on writing to the fdr (see table 9). gate drive output slew rate (inrush current) control the gate output drives an external n-channel fet. the gate pin goes high when no overcurrent, undervoltage or overvoltage conditions exist. the x80000 provides an i gate current of 50a to provide on-chip slew rate control to mi nimize inrush current. this current is programmable from 10a to 160ua (in 10a steps) to allow the x80000 to support various load conditions (see figure 23 and figure 28). i gate is chosen to limit the inrush current and to provide the best charge time for a given load, while avoiding over current conditions. the user programs the i gate current using four i gate control bits. for applications that require different ramp rates during insertion and start-up and operations modes, the x80000 provides two external pins, igq1 and igq0, that allow the user to switch to different gate currents on-the-fly by selecting one of four pre-selected i gate currents. when igq0 and igq1 are left unconnected, the gate current is determined by the gate control bi ts. the other three settings are 10a, 70a and 150a. typically, the delay from igq1 and igq0 selection to a change in the gate pin current is less than 1 second. programmable slew ra te (gate) control as shown in figure 29, this circuit block contains a selectable current source (i gate ) that drives the 50a current into the gate pin. this current provides a controlled slew rate for the fet. x80000 allows the user to change the gate current to one of sixteen possible i gate values. the options allow currents of between 10 a to 160 a in 10 a increments. once the overcurrent condition and the amount of load is known, an appropriate slew rate can be determined and selected for the external fet. this will ensure proper table 6. retry and event sequence options nr2 nr1 nr0 n retry and retry sequence of events (failure mode) 0 0 0 always retry, do not assert far pin (default) 001n retry = 1 (one retry), assert far pin after n retry, stop retry, and shutoff gate pin 010n retry = 2 (two retries), assert far pin after n retry, stop retry, and shutoff gate pin 011n retry = 3 (three retries), assert far pin after n retry, stop retry, and shutoff gate pin 100n retry = 4 (four retries), assert far pin after n retry, stop retry, and shutoff gate pin 101n retry = 5 (five retries), assert far pin after n retry, stop retry, and shutoff gate pin 1 1 0 always retry, assert far pin after 1st retry; clear far when foc cleared, do not shutoff gate pin. 111n retry = 0 (no retry), asset far , and shutoff gate pin. table 7. retry event delay options tsc1 tsc0 t sc_retry , delay between retries 0 0 100 miliseconds 0 1 500 miliseconds 1 0 1 second 1 1 5 seconds table 8. overcurrent flag bit status bit violation (on) normal (off) foc foc = 0, when v rsense > v oc foc = 1, when: v rsense < v oc - 0.2v and reset by a write operation or hardshort retry is initiated. table 9. retry count failure status bit status bit condition far_stat if far_stat = 1, far is asserted. if far_stat = 0, far is deasserted inrush current overcurrent i gate i gate = 160a 100a 75a 25a 10a t1 time (ms) t2 t3 t4 t5 figure 28. selecting i gate current for slew rate control on the gate pin x80000, X80001
21 fn8148.0 march 18, 2005 operation to control inrush currents during hot insertion modes. software slew rate control users can adjust the slew rate control by using an smbus write command to change the slew rate control bits. this allows adaptation in the case of changing load conditions, creates a modular design for downstream dc-dc supplies, and provides control of the load on the hot voltage when slew rates vs. loads vary. gate capacitor, filtering and feedback in figure 29, the fet control circuit includes an fet feedback capacitor c 2 , which provides compensation for the fet during turn on. the capacitor value depends on the load, the fet gate current, and the maximum desired inrush current. the value of c2 can be selected with the following formula: where: i gate = fet gate current i inrush = maximum desire d inrush current c load = dc/dc bulk capacitance with the x80000, there is some control of the gate current with the igq pins and igx bits, so one selection of c2 can cover a wide range of possible loading conditions. typical values for c2 range from 2.2 to 4.7nf. when power is applie d to the system, the fet tries to turn on due to its internal gate to drain capacitance (cgd) and the feedback capacitor c2 (see figure 29). the x80000 device, when powered, pulls the gate out put low to prevent the gate voltage from rising and keep the fet from turning on. however, unless v dd powers up very quickly, there will be a brief period of time during initial application of power when the x80000 circuits cannot hold the gate low. the use of an external capacitor (c1) prevents this. capacitors c1 and c2 form a voltage divider to prevent the gate voltage from rising above the fet turn on threshold before the x80000 can hold the gate low. use the following formula for choosing c1. where: v1 = maximum input voltage, v2 = fet threshold voltage, c1 = gate capacitor, c2 = feedback capacitor. in a system where v dd rises very fast, a smaller value of c1 may suffice as the x80000 will control voltage at the gate before the voltage can rise to the fet turn on threshold. the circuit of figure 29 assumes that the input voltage can rise to 80v before the x80000 sees operational voltage on v dd . if c1 is used then the series resistor r1 will be required to prevent high frequency oscillations. gate current quick selection for applications that require different ramp rates during insertion and start-up and operations modes or those where the serial interface is not available, the x80000 provides two sense v ee r sense load v dd =12v slew selection gate 10a i inrush drain 100k gate current igq1 igq0 -48v control registers sda scl smbus to 160a logic rate quick select logic 100* 100nf* * optional components see section ?gate capacitor, filtering and feedback ? 22k 3.3nf c2 r2 figure 29. programmble slew rate (inrush current) control c2 i gate c load i inrush ------------------------------------------- = table 10. i gate output current options ig3 ig2 ig1 ig0 i gate ( a) 0000 10 0001 20 0010 30 0011 40 0 1 0 0 50 default 0101 60 0110 70 0111 80 1000 90 1001 100 1010 110 1011 120 1100 130 1101 140 1110 150 1111 160 c1 v1 v2 ? v2 --------------------- c 2 = x80000, X80001
22 fn8148.0 march 18, 2005 external pins, igq1 and igq0, that allow the system to switch to different gate current on-the-fly with pre-selected i gate currents. the igq1 and igq0 pins can be used to select from one of four set values. typically, the delay from igq1 and igq0 selection to a change in the gate pin current is less than 1 second. drain sense and power good indicator the x80000 provides a drain sense and power good indicator circuit. the pwrgd signal asserts low when there is no overvoltage, no u ndervoltage, and no overcurrent condition, the gate voltage exceeds vdd-1v, and the voltage at the drain pin is less v ee +v drain . as shown in figure 30, this circuit block contains a drain sense voltage trip point ( ? v drain ) and a gate voltage trip point ( ? v gate ), two comparators, and internal voltage references. these provide both a drain sense and a gate sense circuit to determine the whether the fet has turned on as requested. if so, the power good indicator (pwrgd ) goes active. the drain sense circuit checks the drain pin. if the voltage on this pin is greater that 1v above v ee , then a fault condition exists. the gate sense circuit checks the gate pin. if the voltage on this pin is less than v ee - 1v, then a fault condition exists. the pwrgd signal asserts (logic low) only when all of the below conditions are true: ? there is no overvoltage or no undervoltage condition, (i.e. undervoltage < v ee < overvoltage.) ? there is no overcurrent condition (i.e. v ee - v sense < v oc .) ? the fet is turned on (i.e. v drain < v ee + 1v and v gate > v dd - 1v). power on reset and system reset with delay application of power to the x80000 activates a power on reset circuit that pulls the reset pin active. this signal, if used, provides several benefits. ? it prevents the system microprocessor from starting to operate with insufficient voltage. ? it prevents the processor from operating prior to stabilization of the oscillator. ? it allows time for an fpga to download its configuration prior to initialization of the circuit. ? it prevents communicati on to the eeprom during unstable power conditions, greatly reducing the likelihood of data corruption on power up. the spor/reset circuit is acti vated when all voltages are within specified ranges and the following time-out conditions are met: pwrgd and v1good , v2good , v3good, and v4good . the spor/reset circuit will then wait 100ms and assert the reset pin. the spor delay may be changed by setting the tpor bits in register cr2. the delay can be set to 100 ms, 500 ms, 1 second, or 5 seconds. igq1 pin igq0 pin contents 0 0 defaults to gate current set by ig3:ig0 bits 0 1 gate current is 10 a 1 0 gate current is 70 a 1 1 gate current is 150 a table 11. spor reset delay options tpor1 tpor0 t spor delay before reset assertion 0 0 100 miliseconds (default) 0 1 500 miliseconds 1 0 1 second 1 1 5 seconds (factory programmable) sense v ee r sense load gate drain 100k -48v sda scl smbus pwrgd + ? 1v v ee control/status registers power good logic ? v drain + ? vdd-1v ? v gate figure 30. drain sense and power good indicator x80000, X80001
23 fn8148.0 march 18, 2005 quad voltage monitoring x80000 monitors 4 voltage enable inputs. when the eni (i=1-4) input is detected to be below the input threshold, the output vigood (i = 1 to 4) goes active. the vigood signal is asserted after a delay of 100ms. this delay can be changed on each vigood output individually with bits in register cr3. the delay can be 100ms, 500ms, 1s and 5s. the vigood signal remains active low until eni rises above threshold. once the pwrgd signal is asserted, the power sequencing of the dc-dc modules can commence. reset will go active 100ms after all vigood (i=1 to 4) outputs are asserted. this delay time can be changed by setting bits in register cr2 (see figure 32). as shown in figure 32, this circuit block contains four separate voltage enable inputs, a time delay circuit, and an output driver. manual reset and remote shutdown the manual reset option allows a hardware reset of either the gate control or the pwrgd indicator. these can be used to recover the system in the event of an abnormal operating condition. the remote shutdown feature of the x80000 allows smart power control remotely through the smbus. the host system can either override the control of the fet, thus turning it off, or it can remove the override. removing the override restarts the power up sequence. the x80000 has two manual reset pins: mrh (manual reset hot side) and mrc (manual reset cold side). the mrh signal is used as a manual reset for the gate pin. this pin is used to initiate soft reinsert. when mrh is pulled low the gate pin will be pulled low. it also clears the remote shutdown register (rsr) and the far signal. when the mrh pin goes high, it removes the override signal and the control registers eeprom 2kbits reset logic spor mrc sda v dd drain sense & power good logic enable logic t spor delay reset pwrgd vigood i = 1 to 4 p bus interface scl v ee remote & fault figure 31. power on/system reset and delay (block diagram) table 12. vigood output time delay options tid1 tid0 t delayi 0 0 100ms 0 1 500ms 1 0 1 secs 11 5 secs where i is the ith voltage enable (i = 1 to 4). en1 en2 en3 en4 v4good v3good v2good v1good v ee divider 4 reset osc 0.1s 0.5s 1s 5s select 4 delay1 delay2 delay3 delay4 delay circuit repeated 4 times v rgo control register smbus interface fault detection register figure 32. voltage enable control and vgood outputs x80000, X80001
24 fn8148.0 march 18, 2005 gate will turn on based on the selected gate control mechanism. the mrc signal is used as a manual reset for the pwrgd signal. this pin is used to initiate a soft restart. when the mrc is pulled high, the pwrgd signal is pulled high. when mrc pin goes low, the pwrgd pin goes low using the mrc pin has no affect on the fet gate control, so the fet remains on. fault detection the x80000 contains a fault detection register (fdr) that provides the user the status of the causes for a reset pin active (see table 17). at power-up, the fdr is defaulted to all ?0?. the system needs to initialize the register to all ?1? before the actual monitoring can take place. in the event that any one of the monitored sources fail, the corresponding bit in the register changes from a ?1? to a ?0? to indicate the failure (vigood sources set the bit low when the vigood goes low indicating a ?good? status). when a reset is detected by the main controller, the contro ller should read of the fdr and note the cause of the fault. after reading the register, the controller can reset the register bit back to all ?1? in preparation for future monitored conditions. remote shutdown the gate of the external mosfet can be remotely shutdown by using a software command sequence. a byte write of ?10101010? (aah) data to the remote shutdown register (rsr) will shutdown the gate and the gate will be pulled low. activating the mrh pin or a writing 00h into the rsr will turn off the override signal and the gate will turn on based on the gate control mechanism. the rsr powers up with ?0?s in the register and its contents are volatile. flexible power sequencing of multiple power supplies the x80000 provides several circuits such as multiple voltage enable pins, programmable delays, and a power good signals that can be used to set up flexible power sequencing schemes for do wnstream dc-dc supplies. below are two examples: 1. power up of dc-dc supplies in parallel sequencing using programmable delays on power good (see figure 33 and figure 34). several dc-dc power supplies and their respective power up start times can be controlled using the x80000 such that each of the dc-dc power supplies will start up following the issue of the pwrgd signal. the pwrgd signal is fed into the eni inputs to the x80000. when pwrgd is valid, the internal voltage enable inputs issue vigood signals after a time delay. the vigood signals control the on /off pins of the dc-dc supplies. in the factory default condition, each dc/dc converter is instructed to turn on 100ms after the pwrgd goes active. however, each vigood delay is individually selectable as 100ms, 500ms, 1s and 5s. the delay times are changed via the smbus during calibration of the system. 2. power up of dc-dc supplies via relay sequencing using power good and voltage enables (see figure 35 and figure 36). several dc-dc power supplies and their respective power up start times can be controlled using the x80000 such that each of the dc-dc power supplies will start in a relay sequencing fashion. the 1st dc-dc supply will power up when pwrgd is low after a 100ms delay. subsequent dc-dc supplies will power up after the prior supply has reached its operating voltage. one way to do this is by using an external cpu supervisor (for example the intersil x40430) to monitor the dc-dc output. when the dc/dc voltage is good, th e supervisor output signals the x80000 en1 input to sequence the next supply. an opto-coupler is recommended in this connection for isolation. this configur ation ensures that each subsequent dc-dc supply will power up after the preceding dc-dc supplys voltage output is valid. again, the x80000 offers programmable delays for each voltage enable input that is selectable via the smbus during calibration of the system. table 13. manual reset of th e hot side (gate signal) mrh gate pin requirements 1 operational when mrh is high the manual reset (hot) function is disabled and the device operates normally 0offmrh must be held low minimum of 5 secs to turn of the gate table 14. manual reset of the cold side (pwrgd signal) mrc pwrgd requirements 1 high mrc must be held high minimum of 5 secs to set pwrgd high 0 operational when mrc is low the mrc function is disabled and the device operates normally x80000, X80001
25 fn8148.0 march 18, 2005 v dd v3good en3 v2good en2 v1good en1 pwrgd x80000 v uv/ov v ee sense drain -48v uv=37v ov=71v -48v gate rs 0.02 ? 5% on /off c3 0.1f 100v c4 100f 100v 1 4 v in+ v in- v out + v out sense+ trim sense- + 9 8 7 6 5 reset c v cc1 3.3v on /off c6 0.1f 100v c7 100f 100v 1 4 v in+ v in- v out + v out sense+ trim sense- + 9 8 7 6 5 fpga v cc1 2.5v on /off c9 0.1f 100v c10 100f 100v 1 4 v in+ v in- v out + v out sense+ trim sense- + 9 8 7 6 5 asic v cc1 1.8v r4 182k 1% r5 30k 1% r6 10k 1% q1 irfr120 c5 100f 16v c8 100f 16v c11 100f 16v + + + v4good en4 on /off c12 0.1f 100v c13 100f 100v 1 4 v in+ v in- v out + v out sense+ trim sense- + 9 8 7 6 5 1.2v c14 100f 16v + reset opto coupler pwrgd reset v cc2 v cc2 v cc2 mrh mrc return 100k opto coupler X80001 0.1f 100 4.7k 3.3n -48v return -48v return -48v return -48v return figure 33. typical application of hotswap and dc-dc parallel power sequencing x80000, X80001
26 fn8148.0 march 18, 2005 en2 in t delay1 v1gdo power supply #1 turns on power supply power supply #3 turns on v2gdo 100ms v3gdo programmable delay programmable delay #1 output 500ms 1sec 5sec 100ms 500ms 1sec 5sec t delay2 power supply #2 turns on 100ms 500ms 1sec 5sec t delay3 power supply #2 output power supply #3 output t delay4 programmable delay v4gdo (from pwrgd ) (3.3v) (2.5v) (1.8v) t reset programmable delay reset 100ms 500ms 1sec 5sec 100ms 500ms 1sec 5sec fet turns on select t delayx and t reset via the 2-wire interface. en2 en3 power supply #4 output (1.2v) en4 programmable delay power supply #4 turns on figure 34. parallel sequencing of dc-dc supplies (timing) x80000, X80001
27 fn8148.0 march 18, 2005 v dd v3good en3 v2good en2 v1good en1 pwrgd x80000 v uv/ov v ee sense drain -48v uv=37v ov=71v -48v gate rs 0.02 ? 5% on /off c3 0.1f 100v c4 100f 100v 1 4 v in+ v in- v out + v out sense+ trim sense- + 9 8 7 6 5 3.3v on /off c6 0.1f 100v c7 100f 100v 1 4 v in+ v in- v out + v out sense+ trim sense- + 9 8 7 6 5 2.5v on /off c9 0.1f 100v c10 100f 100v 1 4 v in+ v in- v out + v out sense+ trim sense- + 9 8 7 6 5 1.8v r4 182k 1% r6 10k 1% q1 irfr120 c5 100f 16v c8 100f 16v c11 100f 16v + + + v4good en4 on /off c12 0.1f 100v c13 100f 100v 1 4 v in+ v in- v out + v out sense+ trim sense- + 9 8 7 6 5 1.2v c14 100f 16v + reset opto coupler reset x40430 opto coupler vmon<1:3> vfail<1:3> pwrgd reset c v cc1 fpga v cc1 asic v cc1 v cc2 v cc2 v cc2 mrh mrc r5 30k 1% return 100k opto coupler X80001 (optional) 0.1f 100 4.7k 3.3n -48v return -48v return -48v return -48v return figure 35. typical application of hotswap and dc-dc relay sequencing x80000, X80001
28 fn8148.0 march 18, 2005 control registers and memory the user addressable internal control, status and memory components of the x80000 can be split up into four parts: ? control register (cr) ? fault detection register (fdr) ? remote shutdown register (rsr) ? eeprom array registers the control registers, remote shutdown register and fault detection register are summarized in table 15. changing bits in these registers change the operation of the device or clear fault conditions. reading bits from these registers provides information about device configuration or fault conditions. reads and writes are done through the smbus serial port. it is important to remember that, in most cases, the smbus seri al port must be isolated between the x80000, which is referenced to -48v, and the system controller, which is referenced to ground. en2 in t delay1 v1gdo power supply #1 turns on power supply v2mon threshold power supply #3 turns on v2gdo 100ms v3gdo programmable delay programmable delay #1 output 500ms 1sec 5sec 100ms 500ms 1sec 5sec t delay2 power supply #2 turns on v3mon threshold 100ms 500ms 1sec 5sec t delay3 programmable delay power supply #2 output v4mon power supply #3 output threshold t delay4 programmable delay v4gdo (from pwrgd ) (3.3v) (2.5v) (1.8v) t reset programmable delay reset 100ms 500ms 1sec 5sec 100ms 500ms 1sec 5sec fet turns on select t delayx and t reset via the 2-wire interface. en2 en3 power supply #4 output (1.2v) en4 power supply #4 turns on figure 36. relay sequencing of dc-dc supplies (timing) x80000, X80001
29 fn8148.0 march 18, 2005 all of the control register bits are nonvolatile (except for the wel bit), so they do not change when power is removed. the values of the register block can be read at any time by performing a random read (see serial interface) at the specific byte address location. only one byte is read by each register read operation. bits in the registers can be modified by performing a single byte write operation directly to the address of the register and only one data byte can change for each register write operation. table 15. register address map byte addr. register name description bit memory type 76543210 00h cr0 control register 0 wel0000000volatile 01h cr1 control register 1 wpen 0 0 bp1 bp0 nr2 nr1 nr0 eeprom 02h cr2 control register 2 ig3 ig2 ig1 ig0 tpor1 tpor0 tsc1 tsc0 eeprom 03h cr3 control register 3 t4d1 t4d0 t3d1 t3d0 t2d1 t2d0 t1d1 t1d0 eeprom 04h cr4 control register 4 vs1 vs0 f1 f0 0 0 0 0 eeprom 05h rsr (note 1) remote shutdown register aah: override fet control and shutdown the fet 00h: turn off override (all other data combinations to rsr are reserved.) volatile ff fdr fault detection register fov fuv1/2 foc far_ stat v40s v30s v20s v10s volatile (1) this register is write only table 16. fault detection bits summary symbol location(s) control function/ status indication description register bits far_stat fdr 4 retry violation far_stat = 0 : failure after retry detected (must be preset to 1). foc fdr 5 overcurrent violation foc = 0 : over current detected (must be preset to 1). fov fdr 7 overvoltage violation fov = 0 : over voltage detected (must be preset to 1). fuv1/2 fdr 6 undervoltage violation fuv1/2 = 0 : under voltage detected (must be preset to 1). v1os fdr 0 1st voltage good v1os = 0 : v1good pin has been asserted (must be preset to 1). v2os fdr 1 2nd voltage good v2os = 0 : v2good pin has been asserted (must be preset to 1). v3os fdr 2 3rd voltage good v3os = 0 : v3good pin has been asserted (must be preset to 1). v4os fdr 3 4th voltage good v4os = 0 : v4good pin has been asserted (must be preset to 1). x80000, X80001
30 fn8148.0 march 18, 2005 table 17. hardware/software control and fault detection bits summary symbol location(s) control function/ status indication description register bits software control bits f0 f1 cr4 5:4 insertion current filter f1=0, f0=0 ; t nf = 0 f1=0, f0=1 ; t nf = 5s f1=1, f0=0 ; t nf = 10s f1=1, f0=1 ; t nf = 20s ig0 ig1 ig2 ig3 cr2 7:4 gate current select see table 10. nr0 nr1 nr2 cr1 2:0 retry sequence options see table 6. t1d0 t1d1 cr3 1:0 v1good time delay tid1=0, tid0=0 : vigood delay = 100ms tid1=0, tid0=1 : vigood delay = 500ms tid1=1, tid0=0 : vigood delay = 1s tid1=1, tid0=1 : vigood delay = 5s t2d0 t2d1 cr3 3:2 v2good time delay t3d0 t3d1 cr3 5:4 v3good time delay t4d0 t4d1 cr3 7:6 v4good time delay tpor0 tpor1 cr2 3:2 reset delay time tpor1=0, tpor0=0 : reset delay = 100ms tpor1=0, tpor0=1 : reset delay = 500ms tpor1=1, tpor0=0 : reset delay = 1s tpor1=1, tpor0=1 : reset delay = 5s tsc0 tsc1 cr2 1:0 overcurrent retry delay time tsc1=0, tsc0=0 ; t sc_retry = 100ms tsc1=0, tsc0=1 ; t sc_retry = 500ms tsc1=1, tsc0=0 ; t sc_retry = 1s tsc1=1, tsc0=1 ; t sc_retry = 5s vs0 vs1 cr4 7:6 insertion overcurrent limit vs1=0, vs0=0 ; insertion overcurrent limit = 1x vs1=0, vs0=1 ; insertion overcurrent limit = 2x vs1=1, vs0=0 ; insertion overcurrent limit = 3x vs1=1, vs0=1 ; insertion overcurrent limit = 4x wel cr0 7 write enable wel = 1 enables write operat ions to the control registers and eeprom. wel = 0 prevents write operations. wpen cr1 7 write protect wpen = 1 (and wp pin high) prevents writes to the control registers and the eeprom. bp1 bp0 cr1 4:3 eeprom block protect bp1=0, bp0=0 : no eeprom memory protected. bp1=0, bp0=1 : upper 1/4 of eeprom memory protected bp1=1, bp0=0 : upper 1/2 of eeprom memory protected. bp1=1, bp0=1 : all of eeprom memory protected. hardware select bits igq0 igq1 input pins gate current select igq1=0, igq0=0 : i gate = set by ig0-ig3 igq1=0, igq0=1 : i gate = 10a igq1=1, igq0=0 : i gate = 70a igq1=1, igq0=1 : i gate = 150a batton input pin main or battery batton = 0 ; undervoltage threshold = v uv1 batton = 1 ; undervoltage threshold = v uv2 x80000, X80001
31 fn8148.0 march 18, 2005 memory the x80000 contains a 2kbit eeprom memory array. this array can contain information about manufacturing location and dates, board configuration, fault conditions, service history, etc. access to this memory is through the smbus serial port. read and write operations are similar to those of the control registers, but a si ngle command can write up to 16 bytes at one time. a single read command can return the entire contents of the eeprom memory. register and memory protection in order to reduce the possib ility of inadvertent changes to either a control register of the contents of memory, several protection mechanisms are built into the x80000. these are a write enable latch, block protect bits, a write protect enable bit and a write protect pin. wel: write enable latch a write enable latch (wel) bit controls write accesses to the nonvolatile register s and the eeprom memo ry array in the x80000. this bit is a volatile latch that powers up in the low (disabled) state. while the wel bit is low, writes to any address (registers or memory) will be ignored. the wel bit is set by writing a ?1? to the wel bit and zeroes to the other bits of the control register 0 ( cr0). it is important to write only 00h or 80h to the cr0 register. once set, wel remains set until either it is reset to 0 (by writing a ?0? to the wel bit and zeroes to the other bits of the control register) or until the part powers up again. note, a write to fdr or rsr does not require that wel=1. bp1 and bp0: block protect bits the block protect bits, bp1 and bp0, determines which blocks of the memory array are write protected. a write to a protected block of memory is ignored. the block protect bits will prevent write operations to one of four segments of the array. wpen: write protect enable the write protect pin and write protect enable bit in the cr1 register control the programmable hardware write protect feature. hardware pr otection is enabled when the wp pin is high and wpen bit is high and disabled when wp pin is low or the wpen bit is low. when the chip is hardware write protected, non-v olatile writes to all control registers (cr1, cr2, cr3, and cr4) are disabled including bp bits, the wpen bit itself, and the blocked sections in the memory array. only the section of the memory array that are not block protected can be written. bp1 bp0 protected addresses (size) array lock 0 0 none (default) none (default) 0 1 c0h - ffh (64 bytes) upper 1/4 1 0 80h - ffh (128 bytes) upper 1/2 1 1 00h - ffh (256 bytes) all table 18. write protect conditions wel wp wpen memory array not block protected memory array block protected writes to cr1, cr2, cr3, cr4 protection low x x writes blocked writes bl ocked writes blocked hardware high low x writes enabled writes blocked writes enabled software high high low writes enabled writes blocked writes enabled software high high high writes enabled writes blocked writes blocked hardware x80000, X80001
32 fn8148.0 march 18, 2005 bus interface information interface conventions the device supports a bidirect ional bus oriented protocol. the protocol defines any devic e that sends data onto the bus as a transmitter, and the receiving device as the receiver. the device controlling the transfer is called the master and the device being controlled is called the slave. the master always initiates data transfers, and provides the clock for both transmit and receive operations. therefore, the devices in this family operate as slaves in all applications. it should be noted that the ninth clock cycle of the read operation is not a ?don?t care.? to terminate a read operation, the master must either issue a stop condition during the ninth cycle or hold sda high during the ninth clock cycle and then issue a stop condition. serial clock and data data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions (see figure 37). serial start condition all commands are preceded by th e start condition, which is a high to low transition of sda when scl is high. the device continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. serial stop condition all communications must be terminated by a stop condition, which is a low to high transition of sda when scl is high, followed by a high to low transition of scl. the stop condition is also used to place the device into the standby power mode after a read sequence. serial acknowledge acknowledge is a software convention used to indicate successful data transfer. the transmitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data (see figure 38). the device will respond with an acknowledge after recognition of a start condition and if the correct device identifier and select bits are contained in the slave address byte. if a write operation is selected, the device will respond with an acknowledge after the receipt of each subsequent eight bit word. the device will acknowledge all incoming data and address bytes, except for the slave address byte when the device identifier and/or select bits are incorrect. in the read mode, the device will transmit eight bits of data, release the sda line, then monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is generated by the ma ster, the device will continue to transmit data. the device will terminate further data transmissions if an acknowledge is not detected. the master must then issue a stop condition to return the device to standby mode and place the device into a known state. device addressing addressing protocol overview depending upon the operation to be performed on each of these individual parts, a 1, 2 or 3 byte protocol is used. all operations however must begin with the slave address byte being clocked into the smbus port on the scl and sda pins. the slave address selects t he part of the device to be addressed, and specifies if a read or write operation is to be performed. slave address byte following a start condition, the master must output a slave address byte. this byte consists of three parts: ? the device type identifier which consists of the most significant four bits of the slave address (sa7 - sa4). the scl sda start stop figure 37. valid start and stop conditions data output from transmitter data output from receiver 8 1 9 start acknowledge scl from master figure 38. acknowledge response from receiver x80000, X80001
33 fn8148.0 march 18, 2005 device type identifier must be set to 1010 in order to select the device. ? the next two bits (sa3 - sa2) are slave address bits. the bits received via the smbus are compared to a0 and a1 pins and must match or the communication is aborted. ? the next bit, sa1, selects the device memory sector. there are two addressable sectors: the memory array and the control, fault detection and remote shutdown registers. ? the least significant bit of the slave address (sa0) byte is the r/w bit. this bit defines the operation to be performed. when the r/w bit is ?1?, then a read operation is selected. a ?0? selects a write operation (refer to figure 39). serial write operations in order to perform a write operation to either a control register or the eeprom arra y, the write enable latch (wel) bit must first be set. writes to the wel bit do not cause a high voltage write cycle, so the device is ready for the next operation immediately after the stop condition. byte write for a write operation, the device requires the slave address byte and a word address byte. this gives the master access to any one of the words in the array. after receipt of the word address byte, the device responds with an acknowledge, and awaits the next eight bits of data. after receiving the 8 bits of the data byte, the device again responds with an acknowledge. the master then terminates the transfer by generating a st op condition, at which time the device begins the internal wr ite cycle to the nonvolatile memory. during this internal write cycle, the device inputs are disabled, so the device will not respond to any requests from the master. the sda outp ut is at high impedance. a write to a protected block of memory will suppress the acknowledge bit. page write the device is capable of a p age write operation (see figure 40). it is initiated in the sa me manner as the byte write operation; but instead of termi nating the write cycle after the first data byte is transferred, the master can transmit an unlimited number of 8-bit byte s. after the receipt of each byte, the device will respond with an acknowledge, and the address is internally incremented by one. the page address remains constant. when the counter reaches the end of the page, it ?rolls over? and goes back to ?0? on the same page (see figure 41). this means that the master ca n write 16 bytes to the page starting at any location on that page. if the master begins writing at location 10, and loads 12 bytes, then the first 6 bytes are written to locations 10 through 15, and the last 6 bytes are written to locations 0 through 5. afterwards, the address counter would point to location 6 of the page that was just written. if the master supplies more than 16 bytes of data, then new data overwrites the previous data, one byte at a time. the master terminates the data byte loading by issuing a stop condition, which causes the device to begin the nonvolatile write cycle. as with the byte write operation, all inputs are disabled until completion of the internal write cycle. stop and write modes stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte plus the subsequent ack signal. if a stop is issued in the middle of a data byte, or before 1 full data byte plus its associated ack is sent, then the device will reset itself without performing the write. the contents of th e array will not be effected. acknowledge polling the disabling of the inputs during high voltage cycles can be used to take advantage of the typical 5ms write cycle time. once the stop condition is issued to indicate the end of the master?s byte load operation, the device initiates the internal high voltage cycle. acknowle dge polling can be initiated immediately. to do this, the master issues a start condition followed by the slave address byte for a write or read operation. if the device is st ill busy with the high voltage cycle then no ack will be returned. if the device has completed the write operation, an ack will be returned and the host can then proceed with the read or write operation (see figure 44). sa6 sa7 sa5 sa3 sa2 sa1 sa0 device type identifier read / sa4 r/w 101 0 write address external device memory select a1 a0 ms internal address (sa1) internally addressed device 0eeprom array 1 control register, fault detection register, remote shutdown register bit sa0 operation 0write 1 read figure 39. slave address format x80000, X80001
34 fn8148.0 march 18, 2005 s t a r t s t o p slave address byte address data (n) a c k a c k a c k sda bus signals from the slave signals from the master 0 data (1) a c k (1 to n to 16) 1010 figure 40. page write operation address address 10 5 bytes n-1 7 bytes address = 6 address pointer ends here addr = 7 figure 41. writing 12 bytes to a 16-byte page starting at location 10 0 slave address byte address a c k a c k s t a r t s t o p slave address data a c k 1 s t a r t sda bus signals from the slave signals from the master 1010 1010 figure 42. random address read sequence s t a r t s t o p slave address data sda bus signals from the slave signals from the master 1 a c k 1010 figure 43. current address read sequence x80000, X80001
35 fn8148.0 march 18, 2005 serial read operations read operations are initiated in the same manner as write operations with the exception that the r/w bit of the slave address byte is set to one. there are three basic read operations: current address reads, random reads, and sequential reads. random read random read operation allows the master to access any memory location in the array. prior to issuing the slave address byte with the r/w bit set to one, the master must first perform a ?dummy? write ope ration. the master issues the start condition and the slave address byte, receives an acknowledge, then issues the word address bytes. after acknowledging receipts of the word address bytes, the master immediately issues another start condition and the slave address byte with the r/w bit set to one. this is followed by an acknowledge from the device and then by the eight bit word. the master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. see figure 42 for the address, acknowledge, and data transfer sequence. current address read internally the device contains an address counter that maintains the address of the last word read incremented by one. therefore, if the last read was to address n, the next read operation would access data from address n+1. on power up, the address of the address counter is undefined, requiring a read or write operation for initialization. upon receipt of the slave address byte with the r/w bit set to one, the device issues an acknowledge and then transmits the eight bits of the data byte. the master terminates the read operation when it does not respond with an acknowledge during the ninth clock and then issues a stop condition. see figure 43 or the address, acknowledge, and data transfer sequence. operational notes the device powers-up in the following state: ? the device is in the low power standby state. ? the wel bit is set to ?0?. in th is state, it is not possible to write to the device. ? sda pin is the input mode. data protection the following circuitry has been included to prevent inadvertent writes: ? the wel bit must be set to allow write operations. ? the proper clock count and bit sequence is required prior to the stop bit in order to start a nonvolatile write cycle. ack returned? issue slave address byte (read or write) byte load completed by issuing stop. enter ack polling issue stop issue start no yes high voltage cycle complete. continue command sequence? issue stop no continue normal read or write command sequence proceed yes figure 44. acknowledge polling sequence x80000, X80001
36 fn8148.0 march 18, 2005 packaging information 0.009 (0.23) 0.015 (0.38) 0.185 (4.70) 0.025 (0.65) bsc 0.014 (0.35) 0.029 (0.75) (4.70) 0.185 (4.70) 0.027 (0.70) 0.031 (0.80) 0.000 (0.00) 0.030 (0.76) 0.007 (0.19) 0.009 (0.25) 0.000 (0.00) 0.002 (0.05) 0.271 (6.90) 0.279 (7.10) 0.271 (6.90) 0.279 (7.10) pin 1 indent 32-lead very very thin quad flat no lead package 7mm x 7mm body with 0.65mm lead pitch x80000, X80001
37 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8148.0 march 18, 2005 x80000, X80001

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